|Summary |Design Units |Sequential Statements |Concurrent Statements |Predefined Types |Declarations |

|Resolution and Signatures |Reserved Words |Operators |Predefined Attributes |Standard Packages |

Version 1.5, please report any issues to squire@umbc.edu

Compact Summary of VHDL

This is not intended as a tutorial. This is a quick reference
guide to find the statement or statement syntax you need
to write VHDL code.

VHDL is case insensitive, upper case letters are equivalent to
lower case letters. Reserved words are in lower case by
convention and shown in bold in this document.

Identifiers are simple names starting with a letter and may
have letters and digits. The underscore character is allowed but
not as the first or last character of an identifier.

A comment starts with minus minus, "--", and continues to
the end of the line.

Indentation is used for human readability. The language is free
form with the characters space, tab and new-line being "white space."


  • Design units
  • Sequential Statements
  • Concurrent Statements
  • Predefined Types
  • Declaration Statements
  • Resolution and Signatures
  • Reserved Words
  • Operators
  • Predefined Attributes
  • VHDL standard packages and types
  • Other Links
  • Notation used in this Compact Summary

      Each item has:
              a very brief explanation of possible use.
              a representative, possibly not complete, syntax schema
              one or more samples of actual VHDL code.
      In the syntax statement  [ stuff ]  means zero or one copy of "stuff".
      In some cases "optional" is used to not clutter up the syntax with [[][]].
      In the examples, assume the appropriate declarations for identifiers,
      appropriate enclosing design unit and appropriate context clauses.

    Other Links

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