Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.2 (ISE) - O.61xd Target Family: Virtex5
OS Platform: NT64 Target Device: xc5vlx110t
Project ID (random number) 904da38ed12c4f929af97a4154ebff62.DFB53C1CFB5C451F9E51CD86ED810CD4.5 Target Package: ff1136
Registration ID 204886874_200314014_200316044_666 Target Speed: -1
Date Generated 2013-09-02T17:26:23 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-3610QM CPU @ 2.30GHz CPU Speed 2294 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 28-bit adder=1
Comparators=2
  • 28-bit comparator greater=2
Counters=1
  • 28-bit up counter=1
Registers=9
  • Flip-Flops=9
MiscellaneousStatistics
  • AGG_BONDED_IO=18
  • AGG_IO=18
  • AGG_LOCED_IO=18
  • AGG_SLICE=25
  • NUM_BONDED_IOB=18
  • NUM_BSFULL=37
  • NUM_BSLUTONLY=37
  • NUM_BSUSED=74
  • NUM_BUFG=1
  • NUM_LOCED_IOB=18
  • NUM_LOGIC_O5ANDO6=28
  • NUM_LOGIC_O5ONLY=26
  • NUM_LOGIC_O6ONLY=19
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=26
  • NUM_SLICEL=25
  • NUM_SLICE_CARRY4=14
  • NUM_SLICE_CONTROLSET=2
  • NUM_SLICE_CYINIT=129
  • NUM_SLICE_FF=37
  • NUM_SLICE_UNUSEDCTRL=15
  • NUM_UNUSABLE_FF_BELS=3
NetStatistics
  • NumNets_Active=90
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=4
  • NumNodesOfType_Active_BOUNCEIN=36
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_CLKPIN=10
  • NumNodesOfType_Active_CNTRLPIN=10
  • NumNodesOfType_Active_DOUBLE=99
  • NumNodesOfType_Active_GENERIC=2
  • NumNodesOfType_Active_GLOBAL=6
  • NumNodesOfType_Active_HLONG=10
  • NumNodesOfType_Active_INPUT=184
  • NumNodesOfType_Active_IOBIN2OUT=10
  • NumNodesOfType_Active_IOBINPUT=8
  • NumNodesOfType_Active_IOBOUTPUT=18
  • NumNodesOfType_Active_OUTBOUND=67
  • NumNodesOfType_Active_OUTPUT=61
  • NumNodesOfType_Active_PADINPUT=8
  • NumNodesOfType_Active_PADOUTPUT=10
  • NumNodesOfType_Active_PENT=39
  • NumNodesOfType_Active_PINBOUNCE=51
  • NumNodesOfType_Active_PINFEED=200
  • NumNodesOfType_Active_VLONG=21
  • NumNodesOfType_Vcc_INPUT=54
  • NumNodesOfType_Vcc_KVCCOUT=7
  • NumNodesOfType_Vcc_PINFEED=54
SiteStatistics
  • BUFG-BUFGCTRL=1
  • IOB-IOBM=9
  • IOB-IOBS=9
  • SLICEL-SLICEM=3
SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • IOB=18
  • IOB_INBUF=10
  • IOB_OUTBUF=8
  • IOB_PAD=18
  • SLICEL=25
  • SLICEL_A5LUT=14
  • SLICEL_A6LUT=20
  • SLICEL_AFF=9
  • SLICEL_B5LUT=14
  • SLICEL_B6LUT=17
  • SLICEL_BFF=9
  • SLICEL_C5LUT=14
  • SLICEL_C6LUT=16
  • SLICEL_CARRY4=14
  • SLICEL_CFF=9
  • SLICEL_CYINITGND=1
  • SLICEL_D5LUT=12
  • SLICEL_D6LUT=21
  • SLICEL_DFF=10
 
Configuration Data
SLICEL
  • CLK=[CLK:10] [CLK_INV:0]
SLICEL_AFF
  • AFFINIT=[INIT0:9]
  • AFFSR=[SRLOW:9]
  • CK=[CK:9] [CK_INV:0]
  • LATCH_OR_FF=[FF:9]
  • SYNC_ATTR=[ASYNC:9]
SLICEL_BFF
  • BFFINIT=[INIT0:9]
  • BFFSR=[SRLOW:9]
  • CK=[CK:9] [CK_INV:0]
  • LATCH_OR_FF=[FF:9]
  • SYNC_ATTR=[ASYNC:9]
SLICEL_CFF
  • CFFINIT=[INIT0:9]
  • CFFSR=[SRLOW:9]
  • CK=[CK:9] [CK_INV:0]
  • LATCH_OR_FF=[FF:9]
  • SYNC_ATTR=[ASYNC:9]
SLICEL_DFF
  • CK=[CK:10] [CK_INV:0]
  • DFFINIT=[INIT0:10]
  • DFFSR=[SRLOW:10]
  • LATCH_OR_FF=[FF:10]
  • SYNC_ATTR=[ASYNC:10]
 
Pin Data
BUFG
  • I0=1
  • O=1
BUFG_BUFG
  • I0=1
  • O=1
IOB
  • I=10
  • O=8
  • PAD=18
IOB_INBUF
  • OUT=10
  • PAD=10
IOB_OUTBUF
  • IN=8
  • OUT=8
IOB_PAD
  • PAD=18
SLICEL
  • A=4
  • A2=7
  • A3=7
  • A4=10
  • A5=18
  • A6=18
  • AQ=9
  • AX=1
  • B=1
  • B2=7
  • B3=7
  • B4=9
  • B5=15
  • B6=15
  • BMUX=1
  • BQ=9
  • C2=7
  • C3=7
  • C4=9
  • C5=14
  • C6=14
  • CIN=12
  • CLK=10
  • CMUX=1
  • COUT=12
  • CQ=9
  • D=4
  • D2=6
  • D3=7
  • D4=10
  • D5=18
  • D6=19
  • DMUX=1
  • DQ=10
  • SR=10
SLICEL_A5LUT
  • O5=14
SLICEL_A6LUT
  • A2=7
  • A3=7
  • A4=10
  • A5=18
  • A6=18
  • O6=20
SLICEL_AFF
  • CK=9
  • D=9
  • Q=9
  • SR=9
SLICEL_B5LUT
  • O5=14
SLICEL_B6LUT
  • A2=7
  • A3=7
  • A4=9
  • A5=15
  • A6=15
  • O6=17
SLICEL_BFF
  • CK=9
  • D=9
  • Q=9
  • SR=9
SLICEL_C5LUT
  • O5=14
SLICEL_C6LUT
  • A2=7
  • A3=7
  • A4=9
  • A5=14
  • A6=14
  • O6=16
SLICEL_CARRY4
  • CIN=12
  • CO3=12
  • CYINIT=2
  • DI0=14
  • DI1=14
  • DI2=14
  • DI3=12
  • O0=7
  • O1=8
  • O2=8
  • O3=8
  • S0=14
  • S1=14
  • S2=14
  • S3=14
SLICEL_CFF
  • CK=9
  • D=9
  • Q=9
  • SR=9
SLICEL_CYINITGND
  • 0=1
SLICEL_D5LUT
  • O5=12
SLICEL_D6LUT
  • A2=6
  • A3=7
  • A4=10
  • A5=18
  • A6=19
  • O6=21
SLICEL_DFF
  • CK=10
  • D=10
  • Q=10
  • SR=10
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc5vlx110t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc5vlx110t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc5vlx110t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc5vlx110t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc5vlx110t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc5vlx110t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 45 34 0 0 0 0 0
bitgen 91 90 0 0 0 0 0
edif2ngd 1 1 0 0 0 0 0
map 198 182 0 0 0 0 0
ngc2edif 2 2 0 0 0 0 0
ngdbuild 213 213 0 0 0 0 0
par 183 180 0 0 0 0 0
trce 180 180 0 0 0 0 0
xst 674 658 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-09-02T16:50:58
PROP_intWbtProjectID=DFB53C1CFB5C451F9E51CD86ED810CD4 PROP_intWbtProjectIteration=5
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_AutoTop=true
PROP_DevFamily=Virtex5 PROP_DevDevice=xc5vlx110t
PROP_DevFamilyPMName=virtex5 PROP_DevPackage=ff1136
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-1
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=37 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=9
NGDBUILD_NUM_INV=9 NGDBUILD_NUM_LUT1=27 NGDBUILD_NUM_LUT2=8 NGDBUILD_NUM_LUT3=2
NGDBUILD_NUM_LUT4=28 NGDBUILD_NUM_MUXCY=54 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=31
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=37 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=9
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=9 NGDBUILD_NUM_LUT1=27 NGDBUILD_NUM_LUT2=8
NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_LUT4=28 NGDBUILD_NUM_MUXCY=54 NGDBUILD_NUM_OBUF=8
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=31
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc5vlx110t-1-ff1136 -top=<design_top> -opt_mode=Speed -opt_level=1
-power=NO -iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized
-rtlview=Yes -glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Off -verilog2001=YES -fsm_extract=YES
-fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT -ram_extract=Yes
-ram_style=Auto -rom_extract=Yes -shreg_extract=YES -rom_style=Auto
-auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto
-iobuf=YES -max_fanout=100000 -bufg=32 -register_duplication=YES
-register_balancing=No -optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto
-use_sync_reset=Auto -iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5