countercode Project Status (02/22/2017 - 22:31:58) | |||
Project File: | Counter.xise | Parser Errors: | No Errors |
Module Name: | countercode | Implementation State: | Mapped (Failed) |
Target Device: | xc7a100t-1csg324 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Wed Feb 22 21:58:36 2017 | |
WebTalk Report | Out of Date | Wed Feb 22 22:16:23 2017 | |
WebTalk Log File | Out of Date | Wed Feb 22 22:16:27 2017 |