countercode Project Status (02/22/2017 - 22:31:58)
Project File: Counter.xise Parser Errors: No Errors
Module Name: countercode Implementation State: Mapped (Failed)
Target Device: xc7a100t-1csg324
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateWed Feb 22 21:58:36 2017
WebTalk ReportOut of DateWed Feb 22 22:16:23 2017
WebTalk Log FileOut of DateWed Feb 22 22:16:27 2017

Date Generated: 02/22/2017 - 22:31:58