// Author: Tinoosh Mohsenin // Date: 2/13/2011 // Testbench template for verifying Problems // Use one of the three methods below to verify your design for each homework problem // You need to modify the inputs and the codes to get each method generate the right results `define INPUT_FILEPATH "in.txt" `define OUTPUT_FILEPATH "out.txt" `timescale 1ns/10ps module tbench; //input outputs of the module under test wire [10:0] out; reg [4:0] a; reg [4:0] b; reg [4:0] c; reg [4:0] f; // a counter for the number of the tests // parameters and integers reg enable; parameter TEST_METHOD = 3; parameter PROCESS_TIME = 20; integer fid_in, fid_out, status; problem1 num00 ( .a( a[4:0] ), .b( b[4:0] ), .c( c[4:0] ), .out( out[10:0] ) ); initial begin if (TEST_METHOD == 1) begin // using $monitor command, it shows a and b and c and the output in their // fixed point representation $monitor("Test %d: a= %b.%b, b= %b.%b, c= %b, out= %b.%b\n", f, a[4], a[3:0], b[4:3], b[2:0], c, out[10:4], out[3:0]); // Tests f= 1; a= 5'b00000;b= 5'b00000;c= 5'b00000; //1 // add of zeros #20; f= f+1; a= 5'b00001;b= 5'b00001;c= 5'b00001;//2 // add of least one for each #20; f= f+1; a= 5'b00001;b= 5'b00000;c= 5'b11111;//3 // see if the distance works #20; f= f+1; a= 5'b00000;b= 5'b01000;c= 5'b00001;//4 // see if for negative numbers works #20; f= f+1; a= 5'b10000;b= 5'b00000;c= 5'b11111;//5 // see if for negative numbers works #20; f= f+1; a= 5'b00000;b= 5'b01000;c= 5'b11111;//6 // see if carry propagates #20; f= f+1; a= 5'b10000;b= 5'b10000;c= 5'b00000;//7 //extreme case (min -) #20; f= f+1; a= 5'b00001;b= 5'b00000;c= 5'b00000;//8 //extreme case (min +) #20; f= f+1; a= 5'b01111;b= 5'b01111;c= 5'b11111;//9 //extreme case (max +) #20; f= f+1; a= 5'b10000;b= 5'b10000;c= 5'b00011;//10 #20; f= f+1; a= 5'b01101;b= 5'b10101;c= 5'b10101;//11 #20; f= f+1; a= 5'b01111;b= 5'b01101;c= 5'b11101;//12 #20; f= f+1; a= 5'b00000;b= 5'b01111;c= 5'b01111;//13 #20; f= f+1; a= 5'b01001;b= 5'b01101;c= 5'b11001;//14 #20; f= f+1; a= 5'b01110;b= 5'b01110;c= 5'b01110;//15 #20; end // directly generates inputs and outputs here if (TEST_METHOD == 2) begin #20; a= 5'b00000;b= 5'b00000;c= 5'b00000; #20; $write("a=%b, b=%b, c=%b, out=%b\n", a, b, c, out); #20; a= 5'b00010;b= 5'b00010;c= 5'b00010; #20; $write("a=%b, b=%b, c=%b, out=%b\n", a, b, c, out); #20; end // reads input from a file and writes output to a file if (TEST_METHOD == 3) begin fid_in = $fopen(`INPUT_FILEPATH, "r"); fid_out = $fopen(`OUTPUT_FILEPATH); status = $fscanf(fid_in, "%d %d %d", a, b, c); #PROCESS_TIME; enable=1; #PROCESS_TIME; enable=0; #PROCESS_TIME; status = $fscanf(fid_in, "%d %d %d", a, b, c); $fclose(fid_in); #PROCESS_TIME; enable=1; #PROCESS_TIME; enable=0; #PROCESS_TIME; $fclose(fid_out); $display("done!"); end $finish; // ends simulation end // end initial // write always blocks here always @(posedge enable) $fwrite(fid_out, "%d\n", out); endmodule