`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: UMBC CMPE415 // Engineer: Brian W. Stevens // // Create Date: 13:16:36 02/09/2015 // Design Name: Eight_Bit_Multiplier // Module Name: D:/ExampleProject1/Eight_Bit_Multiplier_tb.v // Project Name: ExampleProject1 // Target Devices: Spartan 3E // Tool versions: Xilinx 13.2 // Description: An awesome example testbench project for an 8-bit multiplier // // Verilog Test Fixture created by ISE for module: Eight_Bit_Multiplier // //////////////////////////////////////////////////////////////////////////////// module Eight_Bit_Multiplier_tb; // Inputs reg signed [7:0] in0; reg signed [7:0] in1; reg clk; // ***Use signed so that monitor/display prints negative numbers // Outputs wire signed [15:0] out; // Test Counter reg [10:0] f; // Instantiate the Unit Under Test (UUT) Eight_Bit_Multiplier uut ( .in0(in0), .in1(in1), .clk(clk), .out(out) ); // Simulate clock with a delay of 1 always #1 clk = ~clk; initial begin // Initialize Inputs in0 = 0; in1 = 0; clk = 0; // Wait 100 ns #100; // Add stimulus here \$monitor("Test %d: in0= %b(%g), in1= %b(%d), out= %b(%d)\n", f, in0, in0, in1, in1, out, out); // Tests f= 0; in0= 8'b00000111;in1= 8'b00010101; //Test 0 // 7*21= 147 #20; f= 1; in0= 14;in1= -3; //Test 1 // 14*-3= -42 #20; f= 2; in0= -1;in1= -3; //Test 2 // -1*-3= 3 #20; end endmodule