The MIPS load and store instructions include both effective address computation and the actual data access. In homework 1, we considered removing the address computation from the data load and store instructions. This would allow merging the EX and DM stages of the MIPS pipeline. Draw the new pipeline datapath with the merged stage. Be sure to think through the paths necessary for each instruction type, and include any additional multiplexers when you need to select between different paths for differing instructions.

4-stage MIPS pipeline: IF ID EX WB


Rework the first example from the Tomasulo slides (code below) for Tomasulo with a Reorder Buffer (ROB). Assume the same number of reservation stations, and the same pipeline latencies as in that example. The description on the slides was a bit sparse, so you will probably need to consult the book or other online sources to fill in the algorithm details. Be sure your answer shows the cycle when each one of the instructions is committed.

LD   F6, 34(R2)
LD   F2, 45(R3)
MULT F0, F2, F4
SUBD F8, F6, F2
DIVD F10, F0, F6
ADDD F6, F8, F2