### Question 1 (20 pts)

Based on this disk drive data, what is the expected disk read time for 1 MiB of data?

### Question 2 (40 pts)

Consider an algorithm that is to be parallelized using message passing. The algorithm will be broken into three phases, A: partition and distribute work, B: compute, and C: collect results. The variables you can control are the number of processors, p, and the number of partitions, w (with w ≥ p). The other factor (which you cannot control) is the size of the problem, n. Given constants KA, KB and KC, the times for these three phases are

• Time(A) = KA w
• Time(B) = KB n/p
• Time(C) = KC n

Where the serial algorithm ran in time

• Time(S) = KB n + KC n
1. What is the speedup of the parallel algorithm?
2. In terms of Amdahl's law, what is the fraction enhanced, fraction unenhanced, and enhanced speedup?
3. What is the optimal choice for w and p?

### Question 3 (40 pts)

The details of the MESIF protocol work much like the 3-state snoopy protocol covered in class. A cache block can be in the Modified state for one and only one core (which can freely read and write it), and must then be Invalid for all other cores

Read-only access is split into three states: Exclusive, Shared and Forwarding. If only one core is accessing a cache block, that block is in the Exclusive state (on a write, the core can switch to Modified without additional messages on the bus). If more than one core is reading the same cache block, that block is in the Shared state on all but the most recent core to request the block. That one core has the cache block in the Forwarding state. Forwarding is just like Shared, except the one core that is marked "Forwarding" will respond to a read miss for the block by forwarding the block directly to the requesting core (faster than going to the next level of cache) and transitioning to Shared (since the new core will take over Forwarding duties for the block).

Based on the description above, draw a state diagram with the five states: Modified, Exclusive, Shared, Invalid, and Forwarding, and the transitions between them. There should be four transitions from each state: for CPU read or write, and Bus read miss or write miss. For each transition, indicate what the core will send on the bus (if anything).