-- fp_add_test.vhdl

-- test bench and "dummy" floating point adder entity (component)


library IEEE;
use IEEE.std_logic_1164.all;
entity fp_add is
  port(a : in  std_logic_vector(31 downto 0);
       b : in  std_logic_vector(31 downto 0);
       s : out std_logic_vector(31 downto 0));
end entity fp_add;


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;   -- arithmetic on std_logic_vector
                                -- to_integer  and  to_StdLogicVectro
architecture behavior of fp_add is
begin  -- behavior of fp_add
  -- compute "s" the IEEE floating point sum of "a" and "b"
  s <= x"01234567" xor a xor b after 1 ns;          -- dummy, remove
end architecture behavior; -- of fp_add

  
entity fp_add_test is                   -- test bench
end fp_add_test;

library STD;
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;

architecture test of fp_add_test is
  signal a : std_logic_vector(31 downto 0) := X"BFECCCCC";
  signal b : std_logic_vector(31 downto 0) := X"3FECCCCC";
  signal s : std_logic_vector(31 downto 0);

  file OUTPUT_FILE : TEXT open write_mode is "fp_add_test.out";

  procedure print_result (
    signal a : in std_logic_vector(31 downto 0);
    signal b : in std_logic_vector(31 downto 0);
    signal s : in std_logic_vector(31 downto 0)) is
    
    variable my_line : LINE;
  begin
    write(my_line, string'("entered print_result"));
    writeline(OUTPUT_FILE, my_line);
    write(my_line, string'("a="));
    hwrite(my_line, a);
    write(my_line, string'("  b="));
    hwrite(my_line, b);
    write(my_line, string'("  s="));
    hwrite(my_line, s);
    writeline(OUTPUT_FILE, my_line);
  end print_result;
    
  component fp_add                      -- copy port from above
    port(a : in  std_logic_vector(31 downto 0);
         b : in  std_logic_vector(31 downto 0);
         s : out std_logic_vector(31 downto 0));
  end component fp_add;
begin  -- test of fp_add_test
  add1 : fp_add port map(a, b, s);
  print_result(a, b, s);
end test;