Write the VHDL code to perform an IEEE 754 32-bit floating point add and test it.
Simplifications you may use include:
As a reminder, normalized IEEE floating point numbers have the following format:
The algorithm for floating point addition is to find the number with the larger exponent, shift the other number to align the mantissas, and perform the operation. Given our simplifications, the resulting exponent will always equal the larger of the operand exponents.
The following instructions assume you will use the machine cadence.gl.umbc.edu to do your work. Instructions for use of the cadence VHDL compiler and simulator can be found at www.csee.umbc.edu/help/VHDL/. Note that (until they're updated) these instructions are for two csee machines for which we no longer have valid cadence licenses. The directions should still work, but you must use cadence.gl.umbc.edu instead of the cs or csee machines mentioned, and use this cs411.tar file rather than the one linked on that page. You may use another machine if you have access to the compiler and simulator there (including using your own machine with one of the free simulators, instructions for one on the help/VHDL page), but if you go that route, be sure to factor in the time to get it working.
You will need to copy any file you are submitting to the gl systems to perform the electronic submit. The submit program does allow you to submit multiple files. Submit all required files (and if appropriate a separate file for the extra credit problem, 3.24) to HW4.