CMSC 411: Computer Architecture

Fall 2015 / 3 credits

MW 1:00-2:15, Sherman 014

Instructor: Dr. Marc Olano (
ITE 354 (455-3094); Office Hours: MW 2:30-3:30

TA: Chayutra Pailom (
ITE 349; Office Hours: 12:00-1:00 MW

Prequisite: C or better in CMSC 313

Text: David Patterson and John Hennessy, Computer Organization and Design, The Hardware/Software Interface, 5th Edition. Morgan Kaufmann, ISBN 978-0124077263


This course covers the design of complex computer systems making heavy use of the components and techniques discussed in CMSC 313 or CMPE 212 and CMPE 310. All parts of the computer system - CPU, memory and input/output - are discussed in detail. Topics include information representation, floating-point arithmetic, instruction set design issues (RISC vs. CISC), microprogrammed control, hardwired control, pipelining, memory caches, bus control and timing, input/output mechanisms and issues in the construction of parallel processors

Course Outcomes

  1. In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary
  2. Broad knowledge of the state of the art in computer architectures
  3. Familiarity with performance metrics and benchmarks
  4. General knowledge of advances in microelectronics and their implication on computer design
  5. Experience the design process in the context of a reasonable size hardware
  6. Exposure to design tools and validation setup


Grades will be based on homework (25%), a team project (25%), a midterm exam (25%) and a final exam (25%).

Homework is due by the begining of class on the date due. Late homework will not be accepted, and will receive a grade of 0.

Academic Honesty

By enrolling in this course, each student assumes the responsibilities of an active participant in UMBC's scholarly community in which everyone's academic work and behavior are held to the highest standards of honesty. Cheating, fabrication, plagiarism, and helping others to commit these acts are all forms of academic dishonesty, and they are wrong.

Specifically for this course, it is acceptable to use the text, instructor and TA. All written homework must be entirely solved and written by you. All programs must consist of either code given to you by the instructor or TA for the class, or code you personally wrote.


Topic dates may shift due to changes in class pace. This schedule will be updated if they do. Text listings show which chapter in the 5th edition of the text covers the concepts from that class. Chapters that are listed across multiple weeks will take us several weeks to cover. Homeworks and components of the project are due at the beginning of class on the dates indicated.

Date Topic Text Due
Aug 26 Introduction Ch. 1
Aug 31/Sep 2 Instruction Representation, Addressing Ch. 2  
Sep 9 Labor Day, Number Representation Ch. 3 HW1 (9/9)
Sep 14/16 Arithmetic, Multiplication, Division, Floating Point Ch. 3  
Sep 21/23 Performance Ch. 1 HW2 (9/23)
Sep 28/30 Datapath Ch. 4 Project (9/30)
Oct 5/7 Hard-wired Control, Microprograms Ch. 4 HW3 (10/7)
Oct 12/14 Review, Midterm Exam
Oct 19/21 Midterm discussion, Pipelining Ch. 4  
Oct 26/28 More Pipelining Ch. 4 Project (10/28)
Nov 2/4 Memory & Cache Ch. 5 HW4 (11/4)
Nov 9/11 More Cache, Virtual Memory Ch. 5 HW5 (11/11)
Nov 16/18 More Virtual Memory, I/O Ch. 5  
Nov 23/25 Bus & I/O Interfaces Ch. 6 Project (11/25)
Nov 30/Dec 2 HDL, GPUs App. B.4, App. C  
Dec 7 Project, Review   Project (12/7)
Dec 16 Final Exam 1:00-3:00    

Online resources