# Homework 5

## CMSC 411 / Olano, Fall 2013

Consider a cache hierarchy with the following stats:

LevelHit TimeMiss Rate Hit RateMiss PenaltyMiss Time
L11 cycle10%
L23 cycles1%
L314 cycles0.1%
Memory120 cycles----
1. Other stats

Fill in the missing columns in the table.

2. Average Memory Access Time

What is the total AMAT for this cache hierarchy?

3. Pipeline timing

Draw two 5-stage MIPS pipeline timing diagrams for the following two instructions: one assuming an L1 hit, and a second assuming an L1 miss but L2 hit.

```     lw  \$1, \$0(data)

Given the address 0x62dc9b38, what are the cache index, offset, and tag, for a 64KB 2-way associative cache with 16-byte cache blocks? What about for a 64KB 8-way associative cache with 16-byte cache blocks?

## Optional Extra Credit

Consider the following 3x3 matrix multiply

```float r, v, m;
for(int j=0; j<3; ++j) {
r[j] = 0.0;
for(int i=0; i<3; ++i) {
r[j] = r[j] + m[j][i]*v[i];
}
}```

Write a simulation of a direct mapped write-back cache. Use this struct to represent a cache line:

```struct CacheLine {
unsigned int tag;
unsigned char data[BLOCKSIZE];
unsigned int validBit;
unsigned int dirtyBit;
}```

Your cache should be an array of these structs. This struct is bigger than the actual cache, since the two bit fields and tag are all represented with full ints, but can tell you the exact number of hits or misses of a real cache with matching parameters. Write two functions, cache_read(address) and cache_write(address) that update the cache structure and print the following as necessary:

```"read  hit  address 0x%08x: index %d, tag 0x%08x, offset %d\n"
"write hit  address 0x%08x: index %d, tag 0x%08x, offset %d\n"
"write miss address 0x%08x: index %d, tag 0x%08x, offset %d\n"
"write back address 0x%08x: index %d, tag 0x%08x, offset %d\n"```

The following modification, embedded into a C program harness, uses &r[j], &m[j][i], and &v[i], to provide a trace of the exact memory locations accessed

```int main() {
int i, j;
float r, v={0}, m={0};
for(j=0; j<3; ++j) {
cache_write(&r[j]);
r[j] = 0.0;
for(i=0; i<3; ++i) {