Homework 4

CMSC 411 / Olano, Spring 2012

Assume a 32-bit processor with cache and memroy with the following stats:

Level Block size Capacity Associativity Write policy Hit/Access time Miss Rate
L1 64 B 32 KB Direct write-back 4 cycles 2.6%
L2 64 B 256 KB 8-way write-back 10 cycles 0.04%
L3 64 B 8 MB 16-way write-back 40 cycles 0.03%
Memory --- 4 GB --- --- 210 cycles ---
  1. How many lines in each cache? Draw the breakdown of bits of a 32-bit address into tag, index and offest at each cache level.
  2. Given the address 0x62dc9b38. What is the word offset into the cache block at each level? What is the index into each level of cache? What tag is stored in each level of cache to uniquely identify the block containing this address?
  3. Counting tags, valid and dirty bits, and data, what is the total actual size of each level of cache?
  4. Give the equation for average memory access time. What is the actual average memory access time given the miss rates in the table.