Homework 3

CMSC 411 / Olano, Spring 2012

In the exam review day, I drew a block diagram to implement the Manchester SSEM in a single cycle, assuming the 32-word memory could be implemented as a register file with two read ports and one write port (i.e. can read two registers during a cycle and write a third at the end of the cycle). I didn't copy down what that diagram looked like, but it was something like the one to the right. Assume instead that, in order to grow the memory size to something significantly longer, we can do a single read and/or write in any one cycle.

  1. Redraw this diagram with the necessary additional temporary registers to run in multiple cycles per instruction, such that you can only read and/or write one value from memory at a time.
  2. Write a multi-cycle Register Transfer Language description for each instruction (refer to the SSEM wikipedia page for the instruction list). Remember you cannot do instruction-specific operations until after you have fetched the instruction!
  3. Draw a state machine for your multi-cycle control.
  4. Revise your RTL description, labelling each state, and clearly indicating the control signals set in each state and the state transitions.