Extra Credit 2

CMSC 411 / Olano, Spring 2012

To the right is a data-flow organization for everybody's least favorite ancient architecture. We want to pipeline this architecture with a three stage pipeline. The first will fetch the instruction from memory. The second will either fetch data from memory or write to memory. The third will perform an ALU operation and store the result in the PC or accumulator.

1. Redraw the diagram with pipeline stages for instruction fetch, memory read/write, and ALU operation drawn from left to right. Include appropriate pipeline registers and forwarding. Assume we can read one addresses and read or write a second address write a single cycle.
2. What structural hazard is present, and how do we solve it?.
3. What data hazard is present, and how do we solve it?
4. What control hazard is present, and how do we solve it?