CMSC 411: Computer Architecture

Spring 2012 / 3 credits

MW 4:00-5:15, ACIV 003

Instructor: Dr. Marc Olano (
ITE 354 (455-3094); Office Hours: MW 2:30-3:45

TA: Debdatta Mukherjee (
ITE 340; Office Hours: MW 1:15-2:30

Prequisite: C or better in CMSC 313 or CMPE 212 & CMPE 310

Text: David Patterson and John Hennessy, Computer Organization and Design, The Hardware/Software Interface, 4th Edition. Morgan Kaufmann, ISBN 978-0-12-374493-7


This course covers the design of complex computer systems making heavy use of the components and techniques discussed in CMSC 313, CMPE 212 and CMPE 310. All parts of the computer system - CPU, memory and input/output - are discussed in detail. Topics include information representation, floating-point arithmetic, instruction set design issues (RISC vs. CISC), microprogrammed control, hardwired control, pipelining, memory caches, bus control and timing, input/output mechanisms and issues in the construction of parallel processors

Course Outcomes

  1. Understand how computer hardware is designed.
  2. Understand how simpler hardware components work together to create a complex computer system.
  3. Understand the issues and implementation of I/O systems.


Grades will be based on homework (20%), a team project (25%), a midterm exam (25%) and a final exam (30%).

Homework is due in class on the date due. Late homework will not be accepted, and will receive a grade of 0. Homeworks should be written or printed out, with your name clearly written at the top of the first page.

Academic Honesty

By enrolling in this course, each student assumes the responsibilities of an active participant in UMBC's scholarly community in which everyone's academic work and behavior are held to the highest standards of honesty. Cheating, fabrication, plagiarism, and helping others to commit these acts are all forms of academic dishonesty, and they are wrong.


Date Topic Due
Jan 30/Feb 1 Instruction Representation, Addressing
Feb 6/8 Number Representation, Arithmetic  
Feb 13/15 Multiplication, Division, Floating Point HW1 (2/15)
Feb 20/22 Performance  
Feb 27/29 Datapath, Single-cycle Control HW2 (2/29)
Mar 5/7 Multi-cycle Control, Microprograms
Mar 12/14 Review, Midterm Exam  
Mar 26/28 Midterm discussion, Pipelining  
Apr 2/4 More Pipelining EC1(4/2), HW3 (4/4)
Apr 9/11 Memory & Cache EC2 (4/9), EC3 (4/11)
Apr 16/18 More Cache, Virtual Memory HW4 (4/18)
Apr 23/25 More Virtual Memory, I/O EC4 (4/23), EC5 (4/25)
Apr 30/May 2 Bus & I/O Interfaces HW5 (5/2)
May 7/9 Advanced Topics, Review Project (5/7)
May 14 Final Exam 3:30-5:30  

Online resources