CMPE 413: Principles of VLSI Design

CMPE 413: Principles of VLSI Design
Section 01
Spring 2022

Instructor: Chintan Patel
Office: ITE 322
Office Hours: Mon & Wed, 4:30 PM - 5:30 PM or by appointment

Teaching Assistants:
Dhandeep Challagundla :
Office Hours: TBD

Meeting Time and Location: TuTh 4:00 - 5:15 PM, ITE 241
Lab Discussion: ITE375, Wed 5:30 - 7:20 MM
Lab: ITE 375, Wed 7:30 - 8:20 PM

Check regularly for important class information

 Syllabus posted.

Course Material

 Syllabus: Spring 2022 syllabus

 Lecture 1: Introduction

 Lecture 2: CMOS Basics I

 Lecture 3: CMOS Basics II

 Lecture 4: IC Technology

 Lecture 5: Circuit and System Representation

 Lecture 6: Quality Metrics I

 Lecture 7: Quality Metrics II

 Lecture 8: MOS Details

 Lecture 9: MOS Capacitance and Resistance Model

 Lecture 10: Inverter DC & AC Response

 Lecture 11: CMOS Fabrication I

 Lecture 12: CMOS Fabrication II

End of Midterm Exam Material

 Lecture 13: Circuit Characterization and Performance Estimation

 Lecture 14: Logical Effort

 Lecture 15: Power Dissipation

 Lecture 16: Interconnect and Wire Engineering

 Lecture 17: Design Margin, Reliability and Scaling

 Lecture 18: Combinational Logic Design

 Lecture 19: Combination Logic Design II

 Lab Submission
  • Completely fill out and include the cover page (doc, html, pdf) with each lab submission.
  • Labs will not be accepted without it.
  • Late submission penalty is 20% lab grade per day late.
  • Weekends will be considered as late days.
 Lab Assignment 1 (Due Fri Feb 11th): Structural VHDL
  • Submit softcopy of the code and report (one pdf file), Use submit command. Class name: cmpe315_cpatel2 , Project name: lab1
  • Code in the report: Use Enscript Command
  • You have to submit a SINGLE pdf file instead of turning in a printed hard copy. It should include the lab cover page. Check the lab description for turning in your code

 Lab Assignment 2 (Due Fri Feb 18th, Extended to Mon Feb ): Schematics and Spectre Simulations

 Lab Assignment 3 (Due Mon Feb 28th): Layout, Extraction and Simulations

 Lab Assignment 4 (Due Wed Mar 16th): D Flip-flop layout and simulations

 Lab Assignment 5 (Due Fri Apr 1st): Import VHDL, layout and LVS


 Project Description

 Project Waveforms

 Example test benches and correct outputs

 Project Submission I Details (VHDL code & Report)

 Instructions for running VNC on ITE375 machines

 Instructions for running cadence tools

 DRC rules for AMI 0.6um technology (Available at MOSIS site)

 Cadence Incisive (VHDL) Tutorial

 Cadence IC6 Tutorials

 Cadence IC5 Tutorials (OLD TOOLS, USE IC6 TUTORIALS)

 VHDL Help