|Summary |Design Structures |Sequential Statements |Concurrent Statements |Types and Constants |
|Declarations |Delay, Events |Reserved Words |Operators |System Tasks |Compiler Directives |
This is not intended as a tutorial. This is a quick reference guide to find the statement or statement syntax you need to write Verilog code. Based on IEEE Standard Verilog Hardware Description Language IEEE Std. 1364-2001 Clause 5.1 page 64 of the Standard says: "Although the Verilog HDL is used for more than just simulation, the semantics of the language are defined for simulation, and everything else is abstracted from this base definition." CAUTION: This information is based on the IEEE standard. Most constructs have been tested on some Verilog compiler, but no compiler, yet, handles the complete standard language. You may not be able to use some features on a specific compiler. Note: many error prone shortcuts have been intentionally omitted.
Verilog is case sensitive
identifiers: start with a letter or underscore "_"
contain letters, numbers, "_" and dollar sign "$"
may contain any non-whitespace escaped character \
comments: // (slash slash) makes the remainder of the line a comment
Each item has:
a very brief explanation of possible use.
a representative, possibly not complete, syntax schema
one or more samples of actual Verilog code.
In the syntax statement <stuff> means zero or one copy of "stuff".
In some cases "optional" is used to not clutter up the syntax.
Reserved words are shown in bold face type.
In the examples, assume the appropriate declarations for identifiers,
appropriate enclosing design unit and appropriate context clauses.
The classic example of a test program for any language is "Hello"
The file hello.v contains:
// hello.v
module hello;
initial
begin
$display("Hello Verilog");
end
endmodule // hello
The command line or graphical user interface to run Verilog
is different for every compiler. You have to get that
information some where else.