Research

VLSI Device Testing

Transient Signal Analysis:

Transient Signal Analysis (TSA) is a testing method that is based on the analysis of a set of VDD port transient waveforms measured simultaneously at each port. Defect detection is performed by applying linear regression analysis to the time or frequency domain representations of these signals. Chip-wide process variation effects introduce signal variations that are correlated across the individual power port measurements. In contrast, defects introduce uncorrelated local variations across these measurements that can be detected as anomalies in the cross-correlation profile derived (using regression analysis) from the power port measurements of defect-free chips. This work focuses on the application of TSA to the detection of delay faults. The ongoing work focuses on three different aspects of TSA.
• Delay Fault Detection
• Delay/performance estimation
• Defect Diagnosis (fault localization)

Quiescent Signal Analysis:

Quiescent Signal Analysis (QSA) is a novel diagnostic and detection technique that uses IDDQ measurements made at multiple supply pads on the Chip-Under-Test as a means of locating shorting defects in the layout. The use of multiple supply pads reduces the adverse effects of leakage current by scaling the total leakage current over multiple simultaneous measurements.

3G-Wireless System Design

W-CDMA Initial Cell Search Design:

In an asynchronous CDMA system the first step when a mobile station is switched on is to perform code and time synchronization with the base station. This process of achieving synchronization with the base station is called initial cell search. The code and time synchronization in the cell search process is divided into three stages: (1) slot boundary detection, (2) code group and frame boundary identification, (3) scrambling code identification.
Our research proposes an Improved Cell Search Design which uses Cyclic Codes (Improved CSD) and compares it to the 3GPP Cell Search Design using Comma Free Codes (3GPP CSD) in terms of a) hardware specifications on a Xilinx Virtex-E FPGA and b) acquisition time measures for different probabilities of false alarm rates. Our results indicate that for a AWGN channel model in a high signal-to-noise ratio environment the Improved CSD scheme requires fewer slots in stage 2 than the 3GPP CSD scheme. The Improved CSD scheme thus achieves faster synchronization with the base station. At the same time the Improved CSD has a lower equivalent gate count as compared to the 3GPP CSD for the same length sequences used in stage 2.

Hardware Prototyping:

Hardware verification of the designs and performance comparison of the cell search algorithms are being carried out on a Xilinx Virtex-E XCV1000E FPGA on a AFX Board. Xilinx Foundation ISE and Synopsys FPGA Express software tools are used for the synthesis and place and route for the FPGA.