ITC University Booth Schedule

Tuesday, September 30^th

Loc/start-time	10:00AM	11:00AM	12:00AM	1:00PM	2:00PM	3:00PM	4:00PM	5:00PM
Desk 1	National Tsing Hua University Memory Failure Analysis Framework Kuo-Liang Cheng Chih-Wea Wang	University of Maryland BC Impedance Profile of a Commercial Power Grid Jitin Tharian	Iowa State University ADC testing Li Jin	University of Maryland BC Path Delay Estimation using Power Supply Transients Abhishek Singh	Technical University of Cluj-Napoca Reliability and Diagnosis Liviu Miclea	Duke University Droplet-Based MicroelectroFuidic Systems Testing Fei SU
Desk2	University of Florida Mixed-signal/RF Embedded Research William Eisenstadt	Tokyo Metropolitan University Application of Partially Rotational Scan Circuit Kazuhiko Iwasaki	Universidade Federal do Rio Grande do Sul Reuse-based Test Planning of Core-based SoCs Erika Cota	Duke University Deterministic BIST Based on a Reconfigurable Interconnection Network Krishnendu Chakrabarty	Politecnico di Torino Automatic Generation of March Tests for Memory Testing Giorgio Di Natale	Politecnico di Torino Integrated Environment for software ImplementeD sysTem faUlt Tolerance Stefano Di Carlo

Wednesday, October 1^st

Loc/start-time	10:00AM	11:00AM	12:00AM	1:00PM	2:00PM	3:00PM	4:00PM	5:00PM
Desk 1	National Tsing Hua University Memory Failure Analysis Framework Kuo-Liang Cheng Chih-Wea Wang	University of Maryland BC Impedance Profile of a Commercial Power Grid Jitin Tharian	Iowa State University ADC testing Li Jin	University of Maryland BC Path Delay Estimation using Power Supply Transients Abhishek Singh	Technical University of Cluj-Napoca Reliability and Diagnosis Liviu Miclea	Duke University Droplet-Based MicroelectroFuidic Systems Testing Fei SU
Desk2	University of Florida Mixed-signal/RF Embedded Research William Eisenstadt	Tokyo Metropolitan University Application of Partially Rotational Scan Circuit Kazuhiko Iwasaki	Universidade Federal do Rio Grande do Sul Reuse-based Test Planning of Core-based SoCs Erika Cota	Duke University Deterministic BIST Based on a Reconfigurable Interconnection Network Krishnendu Chakrabarty	Politecnico di Torino Automatic Generation of March Tests for Memory Testing Giorgio Di Natale	Politecnico di Torino Integrated Environment for software ImplementeD sysTem faUlt Tolerance Stefano Di Carlo

Thursday, October 2^nd

Loc/start-time	10:00AM	11:00AM	12:00AM	1:00PM	2:00PM	3:00PM	4:00PM	5:00PM
Desk 1	National Tsing Hua University Memory Failure Analysis Framework Kuo-Liang Cheng Chih-Wea Wang	University of Maryland BC Impedance Profile of a Commercial Power Grid Jitin Tharian	Iowa State University ADC testing Li Jin	University of Maryland BC Path Delay Estimation using Power Supply Transients Abhishek Singh	Technical University of Cluj-Napoca Reliability and Diagnosis Liviu Miclea	Duke University Droplet-Based MicroelectroFuidic Systems Testing Fei SU
Desk2	University of Florida Mixed-signal/RF Embedded Research William Eisenstadt	Tokyo Metropolitan University Application of Partially Rotational Scan Circuit Kazuhiko Iwasaki	Universidade Federal do Rio Grande do Sul Reuse-based Test Planning of Core-based SoCs Erika Cota	Duke University Deterministic BIST Based on a Reconfigurable Interconnection Network Krishnendu Chakrabarty	Politecnico di Torino Automatic Generation of March Tests for Memory Testing Giorgio Di Natale	Politecnico di Torino Integrated Environment for software ImplementeD sysTem faUlt Tolerance Stefano Di Carlo

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